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12 GHz Microstrip FilterMMIC Oscillator

MMIC Amplifier

Location: /examples/MW_CKTS/MMIC_Amp_prj

Objective

This example shows the design of a 10 GHz, 0.5-Watt balanced amplifier. The finished design consists of two, two-stage amplifiers in parallel. The input signal to the pair of amplifiers is split via a branch line coupler, which is implemented with lumped elements to save space. The outputs from the two amplifiers are combined together via a branch line coupler identical to the one at the input.

This example includes an evaluation of the HEMT devices used in the amplifier, including determination of device transconductance Gm versus bias and load pull analysis.

This example uses elements from a "generic" design kit that was created to show some relatively simple examples of design kit elements. Design kits for real manufacturing processes would have many more elements, and the elements would have more detail, especially the transistors.

Complete Amplifier

Figure 1: Complete Amplifier.

Setup

  1. "FET_Gm_Calcs" simulates the transconductance Gm of a single device, versus bias. This enables you to pick a bias point where the Gm is a maximum to maximize gain.

  2. "FET_SP_NF_Match_Circ" determines the optimal source impedance for minimum noise figure and the corresponding load impedance for maximum gain, both as a function of bias voltage. These impedances are used in the first stage amplifier design where gain is important.
    • Because the first stage device is quite unstable by itself, stabilization networks are added. The R, L, and C values were optimized initially using ideal lumped elements that are shown in "Gain_and_Stab_opt".
    • When these ideal elements are replaced with the equivalent R, L, and C components from the design kit, stability is greatly degraded. So it is necessary to run another optimization using the design kit elements, "Gain_and_Stab_DiscOpt". A discrete value optimization is run to keep the width and spacing of the inductor spiral lines multiples of 1 um and the number of turns an integer.
    • With the stabilization network added, the optimal source and load impedances to present to the stabilized device are determined using "SP_NF_GainMatchK".

  3. "HB1Tone_LoadPullMagPh" simulates the load pull of the second-stage FET. The power-added efficiency varies strongly with the bias point.

  4. "HB1Tone_SourcePull" simulates the source pull of the second-stage FET and indicates that the power delivered to the load does not depend much on the source impedance.

  5. "InputMatch1" determines the ideal lumped-element values for a simple shunt-C, series-L matching network to generate the desired source impedance for the input stage. It uses a Passive Circuit DesignGuide lumped-element matching network component.

  6. "InputMatch_wBias" includes an L-C bias network and design kit elements and a layout with interconnects modeled as traces rather than transmission lines.

  7. "InputMatch_wBias_wTLs" is the result of converting all interconnect traces to transmission lines, and will give the most accurate modeling results, other than using EM simulation. The inductor value has been reduced to compensate for the parasitic inductance of the interconnect transmission lines.

  8. "InterstageMatch1" has a simple shunt-C, series-L matching network generated from the Matching DesignGuide. This transforms the impedance seen looking into the second stage to the desired impedance to present to the first stage.

  9. "InterstageMatch_wBias" includes an L-C bias network and design kit elements, and a layout with the interconnects modeled as traces rather than transmission lines.

  10. "InterstageMatch_wBias_wTLs" is the result of converting most interconnect traces to transmission lines, and will give the most accurate modeling results, other than using EM simulation. The inductor value has been reduced to compensate for the parasitic inductances of the interconnect transmission lines.

  11. "OutputMatch1" is used to determine component values for ideal series-C, shunt-L or series-L, shunt-C networks for generating the desired load impedance for the second stage.

  12. "OutputMatch_wBias" includes an L-C bias network and design kit elements, and a layout with interconnects modeled as traces rather than transmission lines.

  13. "OutputMatch_wBias_wTLs" is the result of converting most interconnect traces to transmission lines, and will give the most accurate modeling results, other than using EM simulation. The inductor value has been reduced to compensate for the parasitic inductances of the interconnect transmission lines.

  14. "TwoStgAmpInZ_TB" uses an S-Probe pair to calculate the reflection coefficients looking both directions at both the input and output planes of the first stage device. The reflection coefficients generated by the input matching network and by the interstage matching network are close to the desired values, and the conditions for oscillation are not satisfied anywhere in the simulated frequency range.

  15. "TwoStgAmpInZ_TB" uses an S-Probe pair to calculate the reflection coefficients looking both directions at both the input and output planes of the first stage device. The reflection coefficients generated by the input matching network and by the interstage matching network are close to the desired values, and the conditions for oscillation are not satisfied anywhere in the simulated frequency range.

  16. "TwoStgAmpOutZ_TB" is the same as "TwoStgAmpInZ_TB", except that the reflection coefficients at the input and output planes of the second stage device are simulated. The desired impedances are generated, and the conditions for oscillation are not satisfied within the simulated frequency range.

  17. "TwoStgAmp_wTLsInZ_TB" is the same as "TwoStgAmpInZ_TB", except that the interconnects are modeled as transmission lines.

  18. "Similarly, "TwoStgAmp_wTLsOutZ_TB" is like "TwoStgAmpOutZ_TB".

  19. "TwoStgAmp_TB" simulates the gain, gain compression, PAE, and other nonlinear characteristics of the two-stage amplifier. It shows a 1-dB gain compression point of about 25 dBm, and a maximum output power of about 26.7 dBm.

  20. "TwoStgAmp_wTLs_TB" is an identical simulation setup, except that all the subcircuits include transmission line effects. It shows a maximum output power of about 26.7 dBm and a 1-dB gain compression point of about 25.2 dBm, but this was only achieved after modifying component values to compensate for the interconnects modeled as transmission lines.

  21. "BLC_LumpedIdeal" is an ideal branch-line coupler, implemented with lumped elements.

  22. "BLC_LumpedIdeal_TB" simulates the "BLC_LumpedIdeal" S-parameters.

  23. "BLC_Lumped" is a branch-line coupler implemented with lumped elements from the design kit.

  24. "BLC_Lumped_TB" simulates the "BLC_Lumped" S-parameters.

  25. "BranchLineCoupDiscOpt" is a discrete-value optimization of the branch-line coupler's inductor parameter values, with transmission line effects included, to minimize insertion loss and optimize the phase difference between the two arms. With transmission line effects included, the optimizer finds that unequal inductor values in the series and shunt arms leads to more optimal performance.

  26. "BLC_Lumped_wTLs" is the result of the optimization.

  27. "BLC_LumpedBk_to_Bk_TB" simulates two optimized branch-line couplers, back-to-back. Ideally the insertion loss should be 0 dB, but the simulated insertion loss is about 1.4 dB. Increasing the drive power overcomes the loss of the input coupler but not the loss of the output coupler.

  28. "BalancedLumpedAmp" is the amplifier without transmission line effects included.

  29. "BalancedLumpedAmp_TB" simulates this amplifier. The maximum output power is about 29 dBm, and the output power at the 1-dB gain compression point is about 26.3 dBm.

  30. "BalancedLumpedAmp_wTLs" is the final amplifier with transmission line effects included.

  31. "BalLumpedAmp_wTLs_TB" simulates this amplifier. The maximum output power is 29.3 dBm and the output power at the 1-dB gain compression point is about 27 dBm.

  32. "BalancedLumpedAmp_wTLs_SP_NF" shows the small-signal S-parameters and noise figure versus frequency. The amplifier has 27 dB of gain, from 9.6 GHz to 10.2 GHz, and a minimum noise figure of about 3 dB.

Simulation Results

Figure 2: Simulation Results.

Notes

  • If you run the Design Rule Checker on the BalancedLumpedAmp design, the only errors you should get are that the widths of the MIM layers must be >= 4 um. This rule is violated by a small margin, by several small capacitors in the layout.